When Hackaday runs a contest, we see all manner of clever projects. But inevitably there are some we don’t see, because their builders didn’t manage to get them finished in time. [Park Frazer]’s phase ...

This application note discusses phase frequency detector characteristics that affect phase-locked loop (PLL) dead band and jitter performance. In PLLs that employ charge pump loop filter designs the ...

Editor's Note: Although the primary target market for the 86100CU-400 application presented below is for ASIC/SoC designs, I'm assured by the folks at Agilent that this application is also applicable ...

But taking a voltage-controlled oscillator at 100 MHz (nominal) and dividing its output by 100 will give you a signal you can lock to a 1 MHz crystal oscillator which is, of course, trivial to build.

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles ...

The NB4N507A is a fully integrated phase lock loop (PLL) designed to replace expensive crystal oscillators for clock generation in a variety of consumer and networking applications. The IC generates a ...

I have always had a soft spot for phase-locked loops – at least, I have since I first found out what they were. What I like about them is that they servo into the best answer for a given situation – ...

Scientists have developed an advanced phase-locked loop (PLL) frequency synthesizer that can drastically cut power consumption. This digital PLL could be an attractive building block for Bluetooth Low ...